1. Field of the Invention
This invention relates to a metal-oxide-semiconductor (MOS) chip and a fabrication method thereof and more particularly relates to a MOS chip featuring a vertical conduction current and a fabrication method thereof.
2. Description of Related Art
According to the direction of conduction current flow, the metal-oxide-semiconductor (MOS) devices can be sorted into planar type and vertical type. For the planar MOS device, the source and the drain are located on the same plane of the semiconductor base for generating a horizontal conduction current. Whereas, the source and the drain of the vertical MOS device are located on the opposing surfaces of the semiconductor base respectively and thus a vertical conduction current is generated.
For the planar MOS device, the withstanding voltage depends on the channel length between the source and the drain. Thus, the planar MOS device always needs a larger area on the semiconductor base for a greater withstanding voltage, which may hinder the improvement of cell density. In contrast, the withstanding voltage of the vertical MOS device depends mainly on the dopant concentration of the semiconductor base. The vertical MOS device can be sorted into the planar gate and the trenched gate according to the location of the gate, wherein the trenched-gate vertical MOS device with the gate electrode being formed in the trench on the semiconductor base is able to shrink the occupied area and is particularly good for increasing cell density.
FIG. 1 is a schematic view of a typical vertical MOS device. A trenched-gate MOS device is shown. As shown, the MOS device is formed on a semiconductor base 110. The semiconductor base 110 is composed of a semiconductor substrate 120 and a lightly-doped epitaxial layer 140 located on the semiconductor substrate 120. The lower surface of the semiconductor base 120 is covered with a metal layer 130 as the drain electrode of the MOS device. The epitaxial layer 140 has a trench 145 formed therein. The gate electrode 160 of the MOS device is located in the trench 145 and isolated from epitaxial layer 140 by a gate oxide layer 162 lining the trench 145. The well 150 is located by the gate electrode 160. The source doped regions 170 are located in the well 150 and electrically isolated from the gate electrode 160 through the gate oxide layer 162. The gate electrode 160 is covered by a dielectric layer 180. The source metal layer 190 is located on the epitaxial layer 140 and the dielectric layer 180 and is electrically connected to the source doped regions 170 and the well 150.
As mentioned, the source electrode and the gate electrode of the vertical MOS device are located on the upper surface of the semiconductor base 110, and the drain electrode thereof is located on the lower surface thereof. Therefore, the bonding pads for the source and the gate electrodes can be fabricated on the front side (the upper surface) of the chip, but the bonding pad for the drain electrode has to be formed on the back side (the lower surface), which results in the difficulty of packaging processes and restricts the applications of the chip.